PIC18F45J10 FAMILY
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
21.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
21.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS (Crystal-Based) modes.
Since the EC mode does not require an OST start-up
delay, Two-Speed Start-up should be disabled.
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS<1:0> bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a POR Reset
is enabled. This allows almost immediate code execu-
tion while the primary oscillator starts and the OST is
running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 21-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTOSC
OSC1
(1)
TOST
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Wake From Interrupt Event
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.
DS39682E-page 244
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
