PIC18F2450/4450
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
BSF
BCF
EECON1, CFGS
EECON1, WREN
INTCON, GIE
; access Flash program memory
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1, WR
Required
Sequence
; write 55h
; write 0AAh
; start program (CPU stall)
DECFSZ COUNTER1
BRA
BSF
BCF
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
; re-enable interrupts
; disable write to memory
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 18.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
See Section 18.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
49
49
49
49
49
51
51
51
51
51
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 Control Register 2 (not a physical register)
EECON1
IPR2
—
CFGS
—
—
FREE
—
WRERR
WREN
HLVDIP
HLVDIF
HLVDIE
WR
—
—
—
—
—
OSCFIP
OSCFIF
OSCFIE
USBIP
USBIF
USBIE
—
—
—
PIR2
—
—
—
PIE2
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 81
MICROCHIP [ MICROCHIP ]
