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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
SUBLW  
Subtract W from Literal  
SUBLW  
SUBWF  
Subtract W from f  
Syntax:  
k
Syntax:  
SUBWF f {,d {,a}}  
Operands:  
Operation:  
Status Affected:  
Encoding:  
Description  
0 k 255  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
k – (W) W  
N, OV, C, DC, Z  
Operation:  
(f) – (W) dest  
0000  
1000  
kkkk  
kkkk  
Status Affected:  
Encoding:  
N, OV, C, DC, Z  
0101 11da  
W is subtracted from the eight-bit  
literal ‘k’. The result is placed in W.  
ffff  
ffff  
Description:  
Subtract W from register ‘f’ (2’s  
complement method). If ‘d’ is ‘0’, the  
result is stored in W. If ‘d’ is ‘1’, the  
result is stored back in register ‘f’  
(default).  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
If ‘a’ is ‘0’, the Access Bank is  
selected. If ‘a’ is ‘1’, the BSR is used  
to select the GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction  
operates in Indexed Literal Offset  
Addressing mode whenever  
f 95 (5Fh). See Section 19.2.3  
“Byte-Oriented and Bit-Oriented  
Instructions in Indexed Literal Offset  
Mode” for details.  
Decode  
Read  
literal ‘k’  
Process  
Data  
Write to W  
Example 1:  
SUBLW 02h  
Before Instruction  
W
C
=
=
01h  
?
After Instruction  
W
C
Z
=
01h  
=
=
=
1
0
0
; result is positive  
N
Words:  
Cycles:  
1
1
Example 2:  
SUBLW 02h  
Before Instruction  
W
C
=
=
02h  
?
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
After Instruction  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
W
C
Z
=
00h  
=
=
=
1
1
0
; result is zero  
N
Example 1:  
SUBWF  
REG, 1, 0  
Before Instruction  
Example 3:  
SUBLW 02h  
REG  
W
=
3
2
?
Before Instruction  
=
=
W
C
=
=
03h  
?
C
After Instruction  
After Instruction  
REG  
W
C
=
1
2
1
0
0
W
C
Z
=
FFh ; (2’s complement)  
=
=
=
=
=
=
=
0
0
1
; result is negative  
; result is positive  
Z
N
N
Example 2:  
SUBWF  
REG, 0, 0  
Before Instruction  
REG  
W
=
=
=
2
2
?
C
After Instruction  
REG  
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero  
Z
N
Example 3:  
SUBWF  
REG, 1, 0  
Before Instruction  
REG  
W
=
=
=
1
2
?
C
After Instruction  
REG  
W
C
=
FFh ;(2’s complement)  
2
0
0
1
=
=
=
=
; result is negative  
Z
N
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 247  
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