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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
ADDWFC  
ADD W and Carry bit to f  
ANDLW  
AND Literal with W  
Syntax:  
ADDWFC  
f {,d {,a}}  
Syntax:  
ANDLW  
k
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operands:  
Operation:  
Status Affected:  
Encoding:  
Description:  
0 k 255  
(W) .AND. k W  
N, Z  
Operation:  
(W) + (f) + (C) dest  
0000  
1011  
kkkk  
kkkk  
Status Affected:  
Encoding:  
N, OV, C, DC, Z  
The contents of W are ANDed with the  
8-bit literal ‘k’. The result is placed in W.  
0010  
00da  
ffff  
ffff  
Description:  
Add W, the Carry flag and data memory  
location ‘f’. If ‘d’ is ‘0’, the result is  
placed in W. If ‘d’ is ‘1’, the result is  
placed in data memory location ‘f’.  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction operates  
in Indexed Literal Offset Addressing  
mode whenever f 95 (5Fh). See  
Section 19.2.3 “Byte-Oriented and  
Bit-Oriented Instructions in Indexed  
Literal Offset Mode” for details.  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read literal  
‘k’  
Process  
Data  
Write to W  
Example:  
ANDLW  
05Fh  
Before Instruction  
W
=
A3h  
03h  
After Instruction  
W
=
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
Example:  
ADDWFC  
REG, 0, 1  
Before Instruction  
Carry bit =  
1
02h  
4Dh  
REG  
W
=
=
After Instruction  
Carry bit =  
0
02h  
50h  
REG  
W
=
=
DS39760A-page 218  
Advance Information  
© 2006 Microchip Technology Inc.