PIC18F2450/4450
FIGURE 15-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 15-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
Start bit
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 2
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
TABLE 15-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
50
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
—
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
—
TXIP
—
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
SPEN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 163
MICROCHIP [ MICROCHIP ]
