PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
8
9
25
26
27
25
26
27
I/O
I
ST
TTL
Digital I/O.
RD
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
AN5
I
Analog
RE1/WR/AN6
RE1
I/O
I
ST
TTL
Digital I/O.
WR
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
AN6
I
Analog
RE2/CS/AN7
RE2
10
I/O
I
ST
TTL
Digital I/O.
CS
Chip Select control for Parallel Slave Port
(see related RD and WR pins).
Analog input 7.
AN7
VSS
I
Analog
—
12, 31 6, 30, 6, 29
31
P
Ground reference for logic and I/O pins.
VDD
11, 32 7, 8, 7, 28
28, 29
P
—
Positive supply for logic and I/O pins.
VDDCORE/VCAP
VDDCORE
VCAP
6
23
23
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
NC
—
13 12,13,
33, 34
—
—
No connect.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39682E-page 21
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