PIC18FXX20
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
U-0
—
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
TMR4IE
R/W-0
CCP5IE
R/W-0
CCP4IE
R/W-0
CCP3IE
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
RC2IE: USART2 Receive Interrupt Enable bit
1= Enables the USART2 receive interrupt
0= Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enables the USART2 transmit interrupt
0= Disables the USART2 transmit interrupt
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 match interrupt
0= Disables the TMR4 to PR4 match interrupt
bit 2-0
CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5)
1= Enables the CCPx interrupt
0= Disables the CCPx interrupt
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 97
MICROCHIP [ MICROCHIP ]
