PIC18FXX20
REGISTER 5-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
EEPGD
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 7
bit 0
bit 7
bit 6
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1= Access FLASH Program memory
0= Access Data EEPROM memory
CFGS: FLASH Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access FLASH Program or Data EEPROM memory
bit 5
bit 4
Unimplemented: Read as '0'
FREE: FLASH Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: FLASH Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any RESET during self-timed programming in normal operation)
0= The write operation completed
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: FLASH Program/Data EEPROM Write Enable bit
1= Allows write cycles to FLASH Program/Data EEPROM
0= Inhibits write cycles to FLASH Program/Data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 63
MICROCHIP [ MICROCHIP ]
