PIC18FXX20
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Details
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on
page:
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register) - value of FSR2 offset by value in WREG
n/a
n/a
57
PREINC2
PLUSW2
57
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 57
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 33, 57
STATUS
TMR0H
TMR0L
—
—
—
N
OV
Z
DC
C
---x xxxx 33, 59
0000 0000 33, 133
xxxx xxxx 33, 133
Timer0 Register High Byte
Timer0 Register Low Byte
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR0ON
T08BIT
—
—
—
—
T0CS
—
IRVST
—
T0SE
—
LVDEN
—
PSA
—
LVDL3
—
T0PS2
—
LVDL2
—
T0PS1
—
LVDL1
—
T0PS0 1111 1111 33, 131
—
—
—
SCS
LVDL0
---- ---0 25, 33
--00 0101 33, 235
SWDTE ---- ---0 33, 250
IPEN
—
RI
TO
PD
POR
BOR
0--1 11qq 33, 60,
101
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx 33, 135
xxxx xxxx 33, 135
T1CON
TMR2
RD16
Timer2 Register
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0-00 0000 33, 135
0000 0000 33, 141
PR2
Timer2 Period Register
1111 1111 33, 142
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 141
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
SSP Receive Buffer/Transmit Register
SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.
xxxx xxxx 33, 157
0000 0000 33, 166
0000 0000 33, 158
2
2
SMP
WCOL
GCEN
CKE
SSPOV
ACKSTAT
D/A
SSPEN
ACKDT
P
CKP
ACKEN
S
R/W
SSPM2
PEN
UA
BF
SSPM3
RCEN
SSPM1
RSEN
SSPM0 0000 0000 33, 159
SEN
0000 0000 33, 169
xxxx xxxx 34, 221
xxxx xxxx 34, 221
--00 0000 34, 213
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
ADFM
—
—
—
CHS3
VCFG1
—
CHS2
VCFG0
—
CHS1
PCFG3
—
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADCS1
ADON
PCFG0 --00 0000 34, 214
ADCS0 0--- -000 34, 215
Capture/Compare/PWM Register1 High Byte
xxxx xxxx 153,
155
CCPR1L
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx 153,
155
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP1M2
CCP2M2
CCP1M1
CCP2M1
CCP1M0 --00 0000 34, 149
xxxx xxxx 34, 153
xxxx xxxx 34, 153
CCP2M0 --00 0000 34, 149
xxxx xxxx 34, 153
Capture/Compare/PWM Register2 High Byte
Capture/Compare/PWM Register2 Low Byte
—
—
DC2B1
DC2B0
Capture/Compare/PWM Register3 High Byte
Capture/Compare/PWM Register3 Low Byte
xxxx xxxx 34, 153
CCP3CON
CVRCON
—
CVREN
—
CVROE
DC3B1
CVRR
DC3B0
CVRSS
CCP3M3
CVR3
CCP3M2
CVR2
CCP3M1
CVR1
CCP3M0 --00 0000 34, 149
CVR0
0000 0000 34, 229
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 53
MICROCHIP [ MICROCHIP ]
