PIC18FXX20
TABLE 4-3:
REGISTER FILE SUMMARY
Details
on
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
page:
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 32, 42
0000 0000 32, 42
0000 0000 32, 42
00-0 0000 32, 43
--10 0000 32, 44
0000 0000 32, 44
0000 0000 32, 44
--00 0000 32, 64
0000 0000 32, 64
0000 0000 32, 64
0000 0000 32, 64
xxxx xxxx 32, 85
xxxx xxxx 32, 85
0000 0000 32, 89
1111 1111 32, 90
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL
—
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
STKUNF
—
—
bit21
Return Stack Pointer
Holding Register for PC<20:16>
(2)
TBLPTRU
—
—
bit21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
INTEDG0 INTEDG1 INTEDG2 INTEDG3
INT1IP INT3IE INT2IE INT1IE
RBIE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
RBPU
INT2IP
INT1IF 1100 0000 32, 91
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
n/a
57
57
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented
(not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
n/a
57
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register) - value of FSR0 offset by value in WREG
n/a
n/a
57
57
PLUSW0
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 57
xxxx xxxx 32, 57
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
xxxx xxxx
32
57
57
n/a
n/a
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
n/a
n/a
n/a
57
57
57
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register)
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register) - value of FSR1 offset by value in WREG
PLUSW1
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 33, 57
xxxx xxxx 33, 57
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
---- 0000 33, 56
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented
(not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
n/a
n/a
57
57
POSTINC2
POSTDEC2
n/a
57
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609A-page 52
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
