欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F8620-I/PT的Datasheet PDF文件第26页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第27页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第28页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第29页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第31页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第32页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第33页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第34页  
PIC18FXX20  
switching currents have been removed, SLEEP mode  
achieves the lowest current consumption of the device  
(only leakage currents). Enabling any on-chip feature  
that will operate during SLEEP, will increase the current  
consumed during SLEEP. The user can wake from  
SLEEP through external RESET, Watchdog Timer  
Reset, or through an interrupt.  
2.7  
Effects of SLEEP Mode on the  
On-Chip Oscillator  
When the device executes a SLEEP instruction, the  
on-chip clocks and oscillator are turned off and the  
device is held at the beginning of an instruction cycle  
(Q1 state). With the oscillator off, the OSC1 and OSC2  
signals will stop oscillating. Since all the transistor  
TABLE 2-3:  
OSC Mode  
OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
OSC1 Pin  
OSC2 Pin  
RC  
Floating, external resistor should pull high  
At logic low  
RCIO  
ECIO  
EC  
Floating, external resistor should pull high  
Configured as PORTA, bit 6  
Configured as PORTA, bit 6  
At logic low  
Floating  
Floating  
LP, XT, and HS  
Feedback inverter disabled, at quiescent  
Feedback inverter disabled, at quiescent  
voltage level  
voltage level  
Note: See Table 3-1 in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.  
With the PLL enabled (HS/PLL Oscillator mode), the  
2.8  
Power-up Delays  
time-out sequence following a Power-on Reset is differ-  
ent from other Oscillator modes. The time-out  
sequence is as follows: First, the PWRT time-out is  
invoked after a POR time delay has expired. Then, the  
Oscillator Start-up Timer (OST) is invoked. However,  
this is still not a sufficient amount of time to allow the  
PLL to lock at high frequencies. The PWRT timer is  
used to provide an additional fixed 2 ms (nominal)  
time-out to allow the PLL ample time to lock to the  
incoming clock frequency.  
Power up delays are controlled by two timers, so that  
no external RESET circuitry is required for most appli-  
cations. The delays ensure that the device is kept in  
RESET until the device power supply and clock are sta-  
ble. For additional information on RESET operation,  
see the “Reset” section.  
The first timer is the Power-up Timer (PWRT), which  
optionally provides a fixed delay of 72 ms (nominal) on  
power-up only (POR and BOR). The second timer is  
the Oscillator Start-up Timer (OST), intended to keep  
the chip in RESET until the crystal oscillator is stable.  
DS39609A-page 28  
Advance Information  
2003 Microchip Technology Inc.  
 复制成功!