PIC18FXX20
REGISTER 23-5: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTEADDRESS300005h)
U-0
—
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
T1OSCMX(1) CCP2MX
bit 0
bit 7-2
bit 1
Unimplemented: Read as ‘0’
T1OSCMX: Timer1 Oscillator Mode bit(1)
1= Standard (legacy) Timer1 oscillator operation
0= Low power Timer1 operation when microcontroller is in SLEEP mode
CCP2MX: CCP2 Mux bit
bit 0
In Microcontroller mode:
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X20 devices only):
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Note 1: Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set.
Legend:
R = Readable bit
- n = Value when device is unprogrammed
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 23-6: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)
R/P-1
DEBUG
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVREN
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
bit 2
Unimplemented: Read as ‘0’
LVP: Low Voltage ICSP Enable bit
1= Low Voltage ICSP enabled
0= Low Voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack Full/Underflow will cause RESET
0= Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit
- n = Value when device is unprogrammed
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 243
MICROCHIP [ MICROCHIP ]
