PIC18FXX20
13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
1:1, 1:4, 1:16
RESET
EQ
TMR2
FOSC/4
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS1:T2CKPS0
4
T2OUTPS3:T2OUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PIE1
IPR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
0000 0000 0000 0000
TMR2
T2CON
PR2
Timer2 Module Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
DS39609A-page 142
Advance Information
2003 Microchip Technology Inc.
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