PIC18FXX20
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
START
START
START
RX (pin)
bit
bit
bit0
bit1
STOP
bit
STOP
bit
bit7/8 STOP bit
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
Word 1
RCREG
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
—
—
ADIF
ADIE
ADIP
—
—
—
RCIF
RCIE
RCIP
RC2IF
RC2IE
RC2IP
SREN
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
(1)
RCSTAx
TXREGx
SPEN
RX9
CREN ADDEN
FERR
OERR
RX9D
(1)
USART Receive Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SPBRGx
SYNC
—
BRGH
TRMT
TX9D
(1)
Legend: x= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and RESET values are identical between modules.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 207
MICROCHIP [ MICROCHIP ]
