PIC18FXX20
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
START bit
bit 0
bit 1
Word 1
bit 7/8
STOP bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
START bit
START bit
Word 2
bit 0
bit 1
Word 1
bit 7/8
bit 0
STOP bit
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
TMR0IF INT0IF
CCP1IF TMR2IF TMR1IF
RBIF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0111 1111 0111 1111
--00 0000 --00 0000
--00 0000 --00 0000
--11 1111 --11 1111
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
TX1IF
TX1IE
TX1IP
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
—
—
IPR3
—
—
(1)
(1)
RCSTAx
SPEN
RX9
SREN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
TXREGx
USART Transmit Register
(1)
TXSTAx
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
(1)
SPBRGx Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and RESET values are identical between modules.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 205
MICROCHIP [ MICROCHIP ]
