PIC18F2331/2431/4331/4431
When TMR1CS = 0, Timer1 increments every instruc-
13.1 Timer1 Operation
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/
T1CKI pins become inputs. That is, the TRISC<1:0>
value is ignored and the pins are read as ‘0’.
The operating mode is determined by the Timer1 Clock
Select bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 16.4.4 “Special Event Trigger”).
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
1
T1OSO/T1CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 13-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T1OSO/T1CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39616D-page 132
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
