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PIC18LF6620-I/PT 参数 Datasheet PDF下载

PIC18LF6620-I/PT图片预览
型号: PIC18LF6620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
the SDO pin is no longer driven, even if in the mid-  
dle of a transmitted byte, and becomes a floating  
output. External pull-up/pull-down resistors may be  
desirable, depending on the application.  
17.3.6  
SLAVE MODE  
In Slave mode, the data is transmitted and received as  
the external clock pulses appear on SCK. When the  
last bit is latched, the SSPIF interrupt flag bit is set.  
While in Slave mode, the external clock is supplied by  
the external clock source on the SCK pin. This external  
clock must meet the minimum high and low times as  
specified in the electrical specifications.  
While in SLEEP mode, the slave can transmit/receive  
data. When a byte is received, the device will wake-up  
from SLEEP.  
Note 1: When the SPI is in Slave mode with SS pin  
control enabled (SSPCON<3:0> = 0100),  
the SPI module will reset if the SS pin is set  
to VDD.  
2: If the SPI is used in Slave mode with CKE  
set, then the SS pin control must be  
enabled.  
When the SPI module resets, the bit counter is forced  
to ‘0’. This can be done by either forcing the SS pin to  
a high level or clearing the SSPEN bit.  
17.3.7  
SLAVE SELECT  
SYNCHRONIZATION  
To emulate two-wire communication, the SDO pin can  
be connected to the SDI pin. When the SPI needs to  
operate as a receiver, the SDO pin can be configured  
as an input. This disables transmissions from the SDO.  
The SDI can always be left as an input (SDI function),  
since it cannot create a bus conflict.  
The SS pin allows a Synchronous Slave mode. The  
SPI must be in Slave mode with SS pin control  
enabled (SSPCON1<3:0> = 04h). The pin must not  
be driven low for the SS pin to function as an input.  
The Data Latch must be high. When the SS pin is  
low, transmission and reception are enabled and  
the SDO pin is driven. When the SS pin goes high,  
FIGURE 17-4:  
SLAVE SYNCHRONIZATION WAVEFORM  
SS  
SCK  
(CKP = 0  
CKE = 0)  
SCK  
(CKP = 1  
CKE = 0)  
Write to  
SSPBUF  
bit6  
bit7  
bit7  
bit0  
SDO  
bit7  
SDI  
bit0  
(SMP = 0)  
bit7  
Input  
Sample  
(SMP = 0)  
SSPIF  
Interrupt  
Flag  
Next Q4 cycle  
SSPSR to  
SSPBUF  
after Q2↓  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 163  
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