PIC18FXX20
12.3 Timer1 Interrupt
12.6 Using Timer1 as a Real-Time
Clock
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2, above) gives users the
option to include RTC functionality to their applications.
This is accomplished with an inexpensive watch crystal
to provide an accurate time-base, and several lines of
application code to calculate the time. When operating
in SLEEP mode and using a battery or supercapacitor
as a power source, it can completely eliminate the need
for a separate RTC device and battery backup.
12.4 Resetting Timer1 using a CCP
Trigger Output
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to incre-
ment a counter at one-second intervals using an Inter-
rupt Service Routine. Incrementing the TMR1 register
pair to overflow, triggers the interrupt and calls the rou-
tine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16-bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never pre-loaded or altered; doing so may
introduce cumulative error over many cycles.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
For this method to be accurate, Timer1 must operate in
Asynchronous mode, and the Timer1 Overflow inter-
rupt must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
12.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
DS39609A-page 138
Advance Information
2003 Microchip Technology Inc.
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