PIC18F2220/2320/4220/4320
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in
Power Managed Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
PSPIF
PSPIE
PSPIP
GIEH/GIE
ADIF
ADIE
ADIP
IPE
IPEN
RCIF
RCIE
RCIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
PSPIF
PSPIE
PSPIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
GIEL\PEIE
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39599C-page 88
2003 Microchip Technology Inc.