PIC18F2220/2320/4220/4320
7.7
Operation During Code-Protect
7.8
Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write opera-
tions are disabled if either of these mechanisms are
enabled.
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
LOOP
BSF
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
; Increment address
BRA
Loop
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADR
EEDATA
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Address Register
EEPROM Data Register
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
RD
xx-0 x000 uu-0 u000
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP CCP2IP 11-1 1111 ---1 1111
TMR3IF CCP2IF 00-0 0000 ---0 0000
TMR3IE CCP2IE 00-0 0000 ---0 0000
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r= reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
DS39599C-page 84
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
