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PIC18LF4320-I/ML 参数 Datasheet PDF下载

PIC18LF4320-I/ML图片预览
型号: PIC18LF4320-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
When a wake-up event occurs, the peripherals continue  
to be clocked from the Timer1 oscillator. After a 10 µs  
delay following the wake-up event, the CPU begins exe-  
cuting code, being clocked by the Timer1 oscillator. The  
microcontroller operates in SEC_RUN mode until the  
primary clock becomes ready. When the primary clock  
becomes ready, a clock switch back to the primary clock  
occurs (see Figure 3-6). When the clock switch is com-  
plete, the T1RUN bit is cleared, the OSTS bit is set and  
the primary clock is providing the system clock. The  
IDLEN and SCS bits are not affected by the wake-up;  
the Timer1 oscillator continues to run.  
3.3.2  
SEC_IDLE MODE  
In SEC_IDLE mode, the CPU is disabled but the  
peripherals continue to be clocked from the Timer1  
oscillator. This mode is entered by setting the IDLEN  
bit, modifying to SCS1:SCS0 = 01 and executing a  
SLEEPinstruction. When the clock source is switched  
to the Timer1 oscillator (see Figure 3-5), the primary  
oscillator is shut down, the OSTS bit is cleared and the  
T1RUN bit is set.  
Note:  
The Timer1 oscillator should already be  
running prior to entering SEC_IDLE mode.  
If the T1OSCEN bit is not set when try-  
ing to set the SCS0 bit (OSCCON<0>),  
the write to SCS0 will not occur. If the  
Timer1 oscillator is enabled but not yet  
running, peripheral clocks will be delayed  
until the oscillator has started; in such sit-  
uations, initial oscillator operation is far  
from stable and unpredictable operation  
may result.  
FIGURE 3-5:  
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE  
Q1 Q2 Q3 Q4 Q1  
1
2
3
4
5
6
7
8
T1OSI  
OSC1  
Clock Transition  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
FIGURE 3-6:  
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)  
Q3  
Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3  
Q1  
Q2  
T1OSI  
OSC1  
(1)  
(1)  
TOST  
TPLL  
PLL Clock  
Output  
1
2
3
4
5
6
7
8
Clock Transition  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC + 4  
PC + 6  
PC  
PC + 2  
OSTS bit Set  
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  
Wake-up from Interrupt Event  
DS39599C-page 34  
2003 Microchip Technology Inc.  
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