PIC18F2220/2320/4220/4320
FIGURE 26-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18FXX20
1.6
3.0
2.0
3.0
11
20(2)
20(2)
6.0
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC mode
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
9.0
µs A/D RC mode
131
TCNV
Conversion Time
12
TAD
(not including acquisition time)(1)
Note 1: ADRES register may be read on the following TCY cycle.
2: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39599C-page 342
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
