PIC18F2220/2320/4220/4320
10.5.1
PORTE IN 28-PIN DEVICES
10.5 PORTE, TRISE and LATE
Registers
For PIC18F2X20 devices, PORTE is only available
when Master Clear functionality is disabled
(CONFIG3H<7> = 0). In these cases, PORTE is a
single bit, input only port comprised of RE3 only. The
pin operates as previously described.
Depending on the particular PIC18F2X20/4X20 device
selected, PORTE is implemented in two different ways.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or out-
puts. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
FIGURE 10-13:
BLOCK DIAGRAM OF
RE2:RE0 PINS
RD LATE
Data
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
Bus
D
Q
WR LATE
or
PORTE
I/O pin(1)
CK
Data Latch
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
D
Q
WR TRISE
RD TRISE
Schmitt
Trigger
Input
CK
TRIS Latch
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Buffer
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
Q
D
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EN
EN
RD PORTE
To Analog Converter
Note 1: I/O pins have diode protection to VDD and VSS.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE con-
figuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
FIGURE 10-14:
BLOCK DIAGRAM OF
MCLR/VPP/RE3 PIN
MCLRE
Data Bus
MCLR/VPP/
RE3
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
RD TRISE
RD LATE
a
Schmitt
Trigger
EXAMPLE 10-5:
CLRF
INITIALIZING PORTE
Latch
D
PORTE
LATE
0x0A
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Q
EN
CLRF
RD PORTE
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
High-Voltage Detect
HV
0x03
; Value used to
; initialize data
; direction
Internal MCLR
Filter
MOVWF
TRISC
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Low-Level
MCLR Detect
2003 Microchip Technology Inc.
DS39599C-page 111
MICROCHIP [ MICROCHIP ]
