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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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PIC18F2220/2320/4220/4320
8.0
8.1
8 X 8 HARDWARE MULTIPLIER
Introduction
Making the 8 x 8 multiplier execute in a single-cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2X20/4X20 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Multiply Method
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
28
52
35
Cycles
(Max)
69
1
91
6
242
28
254
40
Time
@ 40 MHz
6.9
µs
100 ns
9.1
µs
600 ns
24.2
µs
2.8
µs
25.4
µs
4.0
µs
@ 10 MHz
27.6
µs
400 ns
36.4
µs
2.4
µs
96.8
µs
11.2
µs
102.6
µs
16.0
µs
@ 4 MHz
69
µs
1
µs
91
µs
6
µs
242
µs
28
µs
254
µs
40
µs
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
8.2
Operation
EXAMPLE 8-1:
MOVF
MULWF
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
ARG1, W
ARG2
EXAMPLE 8-2:
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
8 x 8 SIGNED MULTIPLY
ROUTINE
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
2003 Microchip Technology Inc.
DS39599C-page 85