PIC18F2220/2320/4220/4320
Timer0 and Timer1 External Clock .......................... 329
U
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
USART ............................................................................. 195
Asynchronous Mode ................................................ 202
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ....................... 203
Receiver .......................................................... 204
Transmitter ...................................................... 202
Baud Rate Generator (BRG) ................................... 198
Associated Registers ....................................... 198
Baud Rate Formula ......................................... 198
Baud Rates, Asynchronous Mode
(INTOSC to HSPLL) ......................................... 247
Transition for Wake from PRI_IDLE Mode ................. 33
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) ..................................... 35
Transition for Wake from SEC_RUN Mode
(HSPLL) ............................................................. 34
Transition for Wake from Sleep (HSPLL) ................... 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive
(BRGH = 0, Low Speed) .......................... 199
Baud Rates, Asynchronous Mode
(BRGH = 1, High Speed) ......................... 200
Baud Rates, Synchronous Mode
(SYNC = 1) .............................................. 201
High Baud Rate Select (BRGH Bit) ................. 198
Operation in Power Managed Mode ................ 198
Sampling .......................................................... 198
Serial Port Enable (SPEN Bit) ................................. 195
Setting Up 9-bit Mode with Address Detect ............. 204
Synchronous Master Mode ...................................... 206
Associated Registers, Reception ..................... 208
Associated Registers, Transmit ....................... 207
Reception ........................................................ 208
Transmission ................................................... 206
Synchronous Slave Mode ........................................ 209
Associated Registers, Receive ........................ 210
Associated Registers, Transmit ....................... 209
Reception ........................................................ 210
Transmission ................................................... 209
(Master/Slave) .................................................. 340
USART Synchronous Reception
(Master Mode, SREN) ...................................... 208
USART SynchronousTransmission
(Master/Slave) .................................................. 340
Timing Diagrams and Specifications ................................ 325
A/D Conversion Requirements ................................ 342
Capture/Compare/PWM Requirements ................... 330
CLKO and I/O Requirements ................................... 327
DC Characteristics - Internal RC Accuracy .............. 326
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 332
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 333
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 334
Example SPI Slave Mode Requirements
V
(CKE = 1) ......................................................... 335
External Clock Requirements .................................. 325
Voltage Reference Specifications .................................... 321
2
W
I C Bus Data Requirements (Slave Mode) .............. 337
2
Master SSP I C Bus Data Requirements ................ 339
Watchdog Timer (WDT) ............................................237, 245
Associated Registers ............................................... 246
Control Register ....................................................... 245
During Oscillator Failure .......................................... 248
Programming Considerations .................................. 245
WCOL .............................................................................. 183
WCOL Status Flag ............................................183, 185, 188
WWW, On-Line Support ...................................................... 5
2
Master SSP I C Bus Start/Stop Bits
Requirements ................................................... 338
Parallel Slave Port Requirements (PIC18F4X20) .... 331
PLL Clock ................................................................. 326
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 328
Timer0 and Timer1 External Clock
X
Requirements ................................................... 329
USART Synchronous Receive
XORLW ............................................................................ 296
XORWF ........................................................................... 297
Requirements ................................................... 340
USART Synchronous Transmission
Requirements ................................................... 340
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 109
TSTFSZ ............................................................................ 296
Two-Speed Start-up ................................................. 237, 247
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 198
2003 Microchip Technology Inc.
DS39599C-page 381
MICROCHIP [ MICROCHIP ]
