PIC18F2220/2320/4220/4320
Timer0 ..............................................................................117
16-bit Mode Timer Reads and Writes ......................119
Associated Registers ...............................................119
Clock Source Edge Select (T0SE Bit) ......................119
Clock Source Select (T0CS Bit) ...............................119
Interrupt ....................................................................119
Operation .................................................................119
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ..............................119
Timer1 ..............................................................................121
16-bit Read/Write Mode ...........................................124
Associated Registers ...............................................125
Interrupt ....................................................................124
Operation .................................................................122
Oscillator .......................................................... 121, 123
Oscillator Layout Considerations .............................123
Overflow Interrupt .....................................................121
Resetting, Using a Special Event
Trigger Output (CCP) .......................................124
Special Event Trigger (CCP) ....................................136
TMR1H Register ......................................................121
TMR1L Register .......................................................121
Use as a Real-Time Clock .......................................124
Timer2 ..............................................................................127
Associated Registers ...............................................128
Operation .................................................................127
Postscaler. See Postscaler, Timer2.
Capture/Compare/PWM (CCP) ............................... 330
CLKO and I/O .......................................................... 327
Clock Synchronization ............................................. 175
Clock, Instruction Cycle ............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 332
Example SPI Master Mode (CKE = 1) ..................... 333
Example SPI Slave Mode (CKE = 0) ....................... 334
Example SPI Slave Mode (CKE = 1) ....................... 335
External Clock (All Modes except PLL) ................... 325
Fail-Safe Clock Monitor (FSCM) .............................. 249
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output ......................................... 145
2
I C Bus Data ............................................................ 336
2
I C Bus Start/Stop Bits ............................................ 336
2
I C Master Mode (Transmission,
7 or 10-bit Address) ......................................... 186
I C Slave Mode (Transmission, 10-bit Address) ...... 173
I C Slave Mode (Transmission, 7-bit Address) ........ 171
I C Slave Mode with SEN = 0
2
2
2
(Reception, 10-bit Address) ............................. 172
I C Slave Mode with SEN = 0
2
(Reception, 7-bit Address) ............................... 170
I C Slave Mode with SEN = 1
2
(Reception, 10-bit Address) ............................. 177
I C Slave Mode with SEN = 1
2
(Reception, 7-bit Address) ............................... 176
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 322
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
2
SSP Clock Shift ................................................ 127, 128
TMR2 Register .........................................................127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Timer3 ..............................................................................129
Associated Registers ...............................................131
Operation .................................................................130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event
Trigger Output (CCP) .......................................131
TMR3H Register ......................................................129
TMR3L Register .......................................................129
Timing Diagrams
Master SSP I C Bus Data ........................................ 338
2
Master SSP I C Bus Start/Stop Bits ........................ 338
Parallel Slave Port (PIC18F4X20) ........................... 331
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 151
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 151
PWM Direction Change ........................................... 148
PWM Direction Change at Near
100% Duty Cycle ............................................. 148
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 328
Slave Mode General Call Address
Sequence (7 or 10-bit Address Mode) ............. 178
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 51
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/
A/D Conversion ........................................................342
Acknowledge Sequence ...........................................188
Asynchronous Reception .........................................205
Asynchronous Transmission ....................................203
Asynchronous Transmission (Back to Back) ............203
Baud Rate Generator with Clock Arbitration ............182
BRG Reset Due to SDA Arbitration
During Start Condition ......................................191
Brown-out Reset (BOR) ...........................................328
Bus Collision During a Repeated
Start Condition (Case 1) ..................................192
Bus Collision During a Repeated
Start Condition (Case 2) ..................................192
Bus Collision During a Stop Condition
(Case 1) ...........................................................193
Bus Collision During a Stop Condition
(Case 2) ...........................................................193
Bus Collision During Start Condition
PLL Enabled (MCLR Tied to VDD) ..................... 51
Time-out Sequence on Power-up
(SCL = 0) ..........................................................191
Bus Collision During Start Condition
(MCLR Not Tied to VDD): Case 1 ....................... 50
Time-out Sequence on Power-up
(SDA Only) .......................................................190
Bus Collision for Transmit and
(MCLR Not Tied to VDD): Case 2 ....................... 50
Time-out Sequence on Power-up
Acknowledge ....................................................189
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 50
DS39599C-page 380
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
