PIC18F2220/2320/4220/4320
22.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 22-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.50V-4.78V
1101= 4.20V-4.46V
1100= 4.00V-4.26V
1011= 3.80V-4.04V
1010= 3.60V-3.84V
1001= 3.50V-3.72V
1000= 3.30V-3.52V
0111= 3.00V-3.20V
0110= 2.80V-2.98V
0101= 2.70V-2.86V
0100= 2.50V-2.66V
0011= 2.40V-2.55V
0010= 2.20V-2.34V
0001= 2.00V-2.12V
0000= Reserved
Note:
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 233