PIC17C75X
FIGURE 6-6: PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W - 0 R/W - 0 R/W - 0
U - 0
—
R/W - 0 R/W - 0
CA4IF CA3IF
R - 1
TX2IF
R - 0
RC2IF
R = Readable bit
SSPIF BCLIF
ADIF
W = Writable bit
-n = Value at POR reset
bit7
bit0
bit 7:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occured, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I C Slave / Master
2
A transmission/reception has taken place.
I C Master
2
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = An SSP interrupt condition has occurred.
bit 6:
bit 5:
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I C master mode
0 = No bus collision has occurred
2
ADIF: A/D Module Interrupt Flag
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
bit 4:
bit 3:
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
bit 2:
bit 1:
bit 0:
CA3IF: Capture3 Interrupt Flag
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag (State controlled by hardware)
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag (State controlled by hardware)
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
DS30264A-page 34
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
