PIC17C4X
TABLRD
Table Read
Table Write
TABLWT
Syntax:
TABLRD 1, 1, REG ;
Example1:
[ label ] TABLWT t,i,f
0 ≤ f ≤ 255
Before Instruction
Operands:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
i
t
[0,1]
[0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem (TBLPTR);
If i = 1,
TBLPTR + 1 → TBLPTR
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
MEMORY(TBLPTR)
Status Affected:
Encoding:
None
TABLRD 0, 0, REG ;
Example2:
1010
11ti
ffff
ffff
Before Instruction
1. Load value in ’f’ into 16-bit table
latch (TBLAT)
Description:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
If t = 0: load into low byte;
If t = 1: load into high byte
2. The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
MEMORY(TBLPTR)
After Instruction (table write completion)
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x55
0x12
0x34
0xA356
0x1234
MEMORY(TBLPTR)
Note: The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be executed, but will not be successful
(although the internal memory location may be
disturbed)
3. The TBLPTR can be automati-
cally incremented
If i = 0; TBLPTR is not
incremented
If i = 1; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write
register
TBLATH or
TBLATL
DS30412C-page 138
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
