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PIC17C752T-25I/P 参数 Datasheet PDF下载

PIC17C752T-25I/P图片预览
型号: PIC17C752T-25I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS微控制器的EPROM [High-Performance 8-Bit CMOS EPROM Microcontrollers]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 320 页 / 2172 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C75X  
2
15.2.9 I C MASTER MODE TRANSMISSION  
15.2.9.1 BF STATUS FLAG  
Transmission of a data byte, a 7-bit address, or the  
either half of a 10-bit address is accomplished by sim-  
ply writing a value to SSPBUF register. This action will  
set the buffer full flag (BF) and allow the baud rate  
generator to begin counting and start the next trans-  
mission. Each bit of address/data will be shifted out  
onto the SDA pin after the falling edge of SCL is  
asserted (see data hold time spec). SCL is held low  
In transmit mode, the BF bit (SSPSTAT<0>) is set  
when the CPU writes to SSPBUF and is cleared when  
all 8 bits are shifted out.  
15.2.9.2 WCOL STATUS FLAG  
If the user writes the SSPBUF when a transmit is  
already in progress (i.e. SSPSR is still shifting out a  
data byte), then WCOL is set and the contents of the  
buffer are unchanged (the write doesn’t occur).  
for one baud rate generator roll over count (T  
).  
BRG  
Data should be valid before SCL is released high (see  
Data setup time spec). When the SCL pin is released  
WCOL must be cleared in software.  
15.2.9.3 AKSTAT STATUS FLAG  
high, it is held that way for T  
, the data on the SDA  
BRG  
pin must remain stable for that duration and some hold  
time after the next falling edge of SCL. After the  
eighth bit is shifted out (the falling edge of the eighth  
clock), the BF flag is cleared and the master releases  
SDA allowing the slave device being addressed to  
respond with an ACK bit during the ninth bit time, if an  
address match occurs or if data was received properly.  
The status of ACK is read into the SSPCON2 register  
bit6 on the falling edge of the ninth clock. If the master  
receives an acknowledge, the acknowledge status bit  
(AKSTAT) is cleared. If not, the bit is set. After the  
ninth clock the SSPIF is set, and the master clock  
(baud rate generator) is suspended until the next data  
byte is loaded into the SSPBUF leaving SCL low and  
SDA unchanged. (Figure 15-29)  
In transmit mode, the AKSTAT bit (SSPCON2<6>) is  
cleared when the slave has sent an acknowledge  
(ACK = 0), and is set when the slave does not  
acknowledge (ACK = 1). A slave sends an acknowl-  
edge when it has recognized its address (including a  
general call), or when the slave has properly received  
its data.  
1997 Microchip Technology Inc.  
Preliminary  
DS30264A-page 149  
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