PIC16F917/916/914/913
Serial Data Out (SDO pin) ........................................193
Slave Select..............................................................193
Slave Select Synchronization ...................................199
Sleep Operation ........................................................201
SPI Clock ..................................................................198
Typical Connection ...................................................197
SSP
Asynchronous Transmission..................................... 124
Asynchronous Transmission (Back-to-Back)............ 124
Brown-out Reset (BOR)............................................ 268
Brown-out Reset Situations ...................................... 223
Capture/Compare/PWM ........................................... 276
CLKOUT and I/O ...................................................... 267
Clock Synchronization .............................................. 209
Clock Timing............................................................. 265
Comparator Output................................................... 109
Fail-Safe Clock Monitor (FSCM)................................. 98
Overview
SPI Master/Slave Connection ...................................197
2
SSP I C Operation............................................................202
2
Slave Mode...............................................................202
SSP Module
I C Bus Data............................................................. 281
2
I C Bus Start/Stop Bits ............................................. 280
2
Clock Synchronization and the CKP Bit....................208
SPI Master Mode ......................................................198
SPI Slave Mode ........................................................199
SSPBUF....................................................................198
SSPSR......................................................................198
SSPCON Register.............................................................195
SSPEN bit .........................................................................195
SSPM bits .........................................................................195
SSPOV bit.........................................................................195
SSPSTAT Register ...........................................................194
STATUS Register................................................................32
Synchronous Serial Port Enable bit (SSPEN)...................195
Synchronous Serial Port Mode Select bits (SSPM) ..........195
Synchronous Serial Port. See SSP
I C Reception (7-bit Address)................................... 204
2
I C Slave Mode (Transmission, 10-bit Address)....... 207
2
I C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 205
I C Transmission (7-bit Address).............................. 206
2
INT Pin Interrupt ....................................................... 232
Internal Oscillator Switch Timing ................................ 94
LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 164
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 166
Reset, WDT, OST and Power-up Timer................... 268
Slave Synchronization .............................................. 199
SPI Master Mode (CKE = 1, SMP = 1) ..................... 278
SPI Mode (Master Mode).......................................... 198
SPI Mode (Slave Mode with CKE = 0)...................... 200
SPI Mode (Slave Mode with CKE = 1)...................... 200
SPI Slave Mode (CKE = 0)....................................... 279
SPI Slave Mode (CKE = 1)....................................... 279
Synchronous Reception (Master Mode, SREN) ....... 138
Synchronous Transmission ...................................... 136
Synchronous Transmission (Through TXEN)........... 136
Time-out Sequence
T
T1CON Register................................................................105
T2CON Register................................................................108
Thermal Considerations....................................................263
Time-out Sequence...........................................................224
Timer0.................................................................................99
Associated Registers ................................................101
External Clock...........................................................100
Interrupt.....................................................................101
Operation ............................................................ 99, 102
Specifications............................................................270
T0CKI........................................................................100
Timer1...............................................................................102
Associated registers..................................................106
Asynchronous Counter Mode ...................................103
Reading and Writing .........................................103
Interrupt.....................................................................104
Modes of Operation ..................................................102
Operation During Sleep ............................................104
Oscillator...................................................................103
Prescaler...................................................................103
Specifications............................................................270
Timer1 Gate
Case 1 .............................................................. 225
Case 2 .............................................................. 225
Case 3 .............................................................. 225
Timer0 and Timer1 External Clock ........................... 270
Timer1 Incrementing Edge ....................................... 104
Two Speed Start-up.................................................... 96
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 154
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 156
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 158
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 160
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 162
Type-A/Type-B in Static Drive .................................. 153
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 155
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 157
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 159
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 161
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 163
USART Synchronous Receive (Master/Slave) ......... 275
USART Synchronous Transmission (Master/Slave). 275
Wake-up from Interrupt............................................. 237
Timing Parameter Symbology .......................................... 264
Timing Requirements
Inverting Gate ...................................................103
Selecting Source.......................................103, 117
Synchronizing COUT w/Timer1 ........................117
TMR1H Register .......................................................102
TMR1L Register........................................................102
Timer2
2
I C Bus Data............................................................. 282
Associated registers..................................................108
Timers
I2C Bus Start/Stop Bits............................................. 281
SPI Mode.................................................................. 280
TRISA
Timer1
T1CON..............................................................105
Timer2
T2CON..............................................................108
Timing Diagrams
Registers .................................................................... 44
TRISA Register................................................................... 44
TRISB
Registers .................................................................... 53
TRISB Register................................................................... 54
TRISC
A/D Conversion.........................................................274
A/D Conversion (Sleep Mode) ..................................274
Asynchronous Reception ..........................................128
DS41250F-page 322
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