PIC16F913/914/916/917/946
3.9.1
PIN DESCRIPTIONS AND
DIAGRAMS
3.9.1.4
RG3/SEG39
Figure 3-30 shows the diagram for this pin. The RG3
pin is configurable to function as one of the following:
Each PORTG pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions,
refer to the appropriate section in this data sheet.
• a general purpose I/O
• an analog output for the LCD
3.9.1.5
RG4/SEG40
3.9.1.1
RG0/SEG36
Figure 3-30 shows the diagram for this pin. The RG4
pin is configurable to function as one of the following:
Figure 3-30 shows the diagram for this pin. The RG0
pin is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog output for the LCD
• an analog output for the LCD
3.9.1.6
RG5/SEG41
3.9.1.2
RG1/SEG37
Figure 3-30 shows the diagram for this pin. The RG5
pin is configurable to function as one of the following:
Figure 3-30 shows the diagram for this pin. The RG1
pin is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog output for the LCD
• an analog output for the LCD
3.9.1.3
RG2/SEG38
Figure 3-30 shows the diagram for this pin. The RG2
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
FIGURE 3-30:
BLOCK DIAGRAM OF RG<5:0>
VDD
Data Bus
D
Q
Q
WR PORTG
CK
I/O Pin
VSS
Data Latch
D
Q
Q
WR TRISG
CK
TRIS Latch
SE<41:36> and LCDEN
RD TRISG
Schmitt
Trigger
RD PORTG
SE<41:36> and LCDEN
SEG<41:36>
© 2007 Microchip Technology Inc.
DS41250F-page 85
MICROCHIP [ MICROCHIP ]
