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PIC16F913-I/SP 参数 Datasheet PDF下载

PIC16F913-I/SP图片预览
型号: PIC16F913-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28 / 44/ 64引脚基于闪存的8位CMOS微控制器与LCD驱动器和纳瓦技术 [28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology]
分类和应用: 驱动器闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 330 页 / 6045 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F913/914/916/917/946  
EXAMPLE 3-7:  
INITIALIZING PORTG  
3.9  
PORTG and TRISG Registers  
BANKSELPORTG  
CLRF PORTG  
BANKSELTRISG  
;
PORTG is an 8-bit port with Schmitt Trigger input  
buffers. RG<5:0> are individually configured as inputs  
or outputs, depending on the state of the port direction.  
The port bits are also multiplexed with LCD segment  
functions. PORTG is available on the PIC16F946 only.  
;Init PORTG  
;
;Set RG<5:0> as inputs  
;
MOVLW  
MOVWF  
3Fh  
TRISG  
REGISTER 3-16: PORTG: PORTG REGISTER(1)  
U-0  
U-0  
R/W-x  
RG5  
R/W-x  
RG4  
R/W-x  
RG3  
R/W-x  
RG2  
R/W-x  
RG1  
R/W-x  
RG0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7-6  
bit 5-0  
Unimplemented: Read as ‘0’  
RG<5:0>: PORTG I/O Pin bits  
1= Port pin is >VIH min.  
0= Port pin is <VIL max.  
Note 1: PIC16F946 only.  
REGISTER 3-17: TRISG: PORTG TRI-STATE REGISTER(1)  
U-0  
U-0  
R/W-1  
R/W-1  
R/W-1  
R/W-1  
R/W-1  
R/W-1  
TRISG5  
TRISG4  
TRISG3  
TRISG2  
TRISG1  
TRISG0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7-6  
bit 5-0  
Unimplemented: Read as ‘0’  
TRISF<5:0>: PORTG Tri-State Control bits  
1= PORTG pin configured as an input (tri-stated)  
0= PORTG pin configured as an output  
Note 1: PIC16F946 only.  
DS41250F-page 84  
© 2007 Microchip Technology Inc.  
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