PIC16F913/914/916/917/946
2.2.2.7
PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0
OSFIF
bit 7
R/W-0
C2IF
R/W-0
C1IF
R/W-0
LCDIF
U-0
—
R/W-0
LVDIF
U-0
—
R/W-0
CCP2IF(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
OSFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= System clock operating
C2IF: Comparator C2 Interrupt Flag bit
1= Comparator output (C2OUT bit) has changed (must be cleared in software)
0= Comparator output (C2OUT bit) has not changed
C1IF: Comparator C1 Interrupt Flag bit
1= Comparator output (C1OUT bit) has changed (must be cleared in software)
0= Comparator output (C1OUT bit) has not changed
LCDIF: LCD Module Interrupt bit
1= LCD has generated an interrupt
0= LCD has not generated an interrupt
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIF: Low Voltage Detect Interrupt Flag bit
1= LVD has generated an interrupt
0= LVD has not generated an interrupt
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit(1)
Capture Mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Note 1: PIC16F914/PIC16F917/PIC16F946 only.
DS41250F-page 38
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
