PIC16F913/914/916/917/946
10.4 LCD Multiplex Types
10.7 LCD Frame Frequency
The LCD driver module can be configured into one of
four multiplex types:
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
• Static (only COM0 is used)
TABLE 10-3: FRAME FREQUENCY
FORMULAS
• 1/2 multiplex (COM<1:0> are used)
• 1/3 multiplex (COM<2:0> are used)
• 1/4 multiplex (COM<3:0> are used)
Multiplex
Frame Frequency =
Static
1/2
Clock source/(4 x 1 x (LP<3:0> + 1))
Clock source/(2 x 2 x (LP<3:0> + 1))
Clock source/(1 x 3 x (LP<3:0> + 1))
Clock source/(1 x 4 x (LP<3:0> + 1))
The LMUX<1:0> bit setting of the LCDCON register
decides the function of RB5, RA2 or either RA3 or RD0
pins (see Table 10-2 for details).
1/3
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
1/4
Note:
Clock source is FOSC/8192, T1OSC/32 or
LFINTOSC/32.
Note:
On a Power-on Reset, the LMUX<1:0>
bits of the LCDCON register are ‘11’.
TABLE 10-4: APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
TABLE 10-2: RA3/RD0, RA2, RB5
FUNCTION
32.768 kHz OR LFINTOSC
LMUX
<1:0>
Multiplex
RA3/RD0(1)
RA2
RB5
LP<3:0>
Static
1/2
1/3
1/4
Static
1/2
00
01
10
11
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
2
3
4
5
6
7
85
64
51
43
37
32
85
64
51
43
37
32
114
85
68
57
49
43
85
64
51
43
37
32
COM1 Driver
1/3
COM2 Driver COM1 Driver
1/4
COM3 Driver COM2 Driver COM1 Driver
Note 1:
RA3 for PIC16F913/916, RD0 for PIC16F914/917 and
PIC16F946
10.5 Segment Enables
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
Note:
On a Power-on Reset, these pins are
configured as digital I/O.
10.6 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 10-4 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
© 2007 Microchip Technology Inc.
DS41250F-page 149
MICROCHIP [ MICROCHIP ]
