PIC16F913/914/916/917/946
10.2.1
LCD PRESCALER
10.2 LCD Clock Source Selection
A 4-bit counter is available as a prescaler for the LCD
clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits of the LCDPS register,
which determine the prescaler assignment and prescale
ratio.
The LCD driver module has 3 possible clock sources:
• FOSC/8192
• T1OSC/32
• LFINTOSC/32
The first clock source is the system clock divided by
8192 (FOSC/8192). This divider ratio is chosen to
provide about 1 kHz output when the system clock is
8 MHz. The divider is not programmable. Instead, the
LCD prescaler bits LP<3:0> of the LCDPS register are
used to set the LCD frame clock rate.
The prescale values are selectable from 1:1 through
1:16.
10.3 LCD Bias Types
The LCD driver module can be configured into one of
three bias types:
The second clock source is the T1OSC/32. This also
gives about 1 kHz when a 32.768 kHz crystal is used
with the Timer1 oscillator. To use the Timer1 oscillator
as a clock source, the T1OSCEN bit of the T1CON
register should be set.
• Static Bias (2 voltage levels: VSS and VDD)
• 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD)
• 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD
and VDD)
The third clock source is the 31 kHz LFINTOSC/32,
which provides approximately 1 kHz output.
This module uses an external resistor ladder to
generate the LCD bias voltages.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
The external resistor ladder should be connected to the
VLCD1 pin (Bias 1), VLCD2 pin (Bias 2), VLCD3 pin
(Bias 3) and VSS. The VLCD3 pin should also be
connected to VDD.
Using bits CS<1:0> of the LCDCON register can select
any of these clock sources.
Figure 10-2 shows the proper way to connect the
resistor ladder to the Bias pins..
Note:
VLCD pins used to supply LCD bias voltage
are enabled on power-up (POR) and must
be disabled by the user by clearing the
VLCDEN bit of the LCDCON register.
FIGURE 10-2:
LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
Static
Bias
1/2 Bias
1/3 Bias
VLCD 0
VLCD 1
VLCD 2
VLCD 3
VSS
—
VSS
1/2 VDD
1/2 VDD
VDD
VSS
1/3 VDD
2/3 VDD
VDD
VLCD 3
VLCD 2
VLCD 1
VLCD 0
To
LCD
Driver
—
(1)
VDD
LCD Bias 3
LCD Bias 2
LCD Bias 1
Connections for External R-ladder
Static Bias
VDD*
VDD*
1/2 Bias
10 kΩ*
10 kΩ*
10 kΩ*
10 kΩ*
VSS
1/3 Bias
10 kΩ*
VDD*
VSS
*
These values are provided for design guidance only and should be optimized for the application
by the designer.
Note 1: Internal connection.
DS41250F-page 148
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
