PIC16F913/914/916/917/946
FIGURE 9-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 9-7:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
Resets
Value on
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE
PEIE
SLPEN
SE14
ADIE
T0IE
INTE
RBIE
CS1
T0IF
CS0
INTF
LMUX1
SE9
RBIF
LMUX0
SE8
0000 000x 0000 000x
0001 0011 0001 0011
0000 0000 0000 0000
LCDCON
LCDSE1
PIE1
LCDEN
SE15
EEIE
WERR VLCDEN
SE13
RCIE
RCIF
SE12
TXIE
TXIF
SE11
SSPIE
SSPIF
SE10
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0000 0000 0000 0000
PIR1
EEIF
ADIF
RCREG
RCSTA
SSPCON
TRISC
AUSART Receive Data Register
SPEN
WCOL
RX9
SREN
CREN
CKP
ADDEN
SSPM3
FERR
OERR
RX9D
0000 000X 0000 000X
SSPOV
SSPEN
SSPM2
SSPM1
SSPM0 0000 0000 0000 0000
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
TXSTA
Legend:
—
DS41250F-page 138
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
