PIC16F913/914/916/917/946
9.3.1.2
Synchronous Master Transmission
9.3
AUSART Synchronous Mode
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the AUSART is configured for
synchronous master transmit operation.
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary cir-
cuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the inter-
nal clock generation circuitry.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the pre-
vious character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
There are two signal lines in Synchronous mode: a bidi-
rectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The AUSART can operate as either a master or slave
device.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Start and Stop bits are not used in synchronous
transmissions.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
9.3.1
SYNCHRONOUS MASTER MODE
9.3.1.3
Synchronous Master Transmission
Set-up:
The following bits are used to configure the AUSART
for Synchronous Master operation:
1. Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (see
Section 9.2 “AUSART Baud Rate Generator
(BRG)”).
• SYNC = 1
• CSRC = 1
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
The LCD SEG8 and SEG9 functions must be disabled
by clearing the SE8 and SE9 bits of the LCDSE1
register, if the RX/DT and TX/CK pins are shared with
the LCD peripheral.
8. Start transmission by loading data to the TXREG
register.
9.3.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the AUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are gener-
ated as there are data bits.
© 2007 Microchip Technology Inc.
DS41250F-page 135
MICROCHIP [ MICROCHIP ]
