PIC16F913/914/916/917/946
REGISTER 10-1: LCDCON: LIQUID CRYSTAL DISPLAY CONTROL REGISTER
R/W-0
R/W-0
R/C-0
R/W-1
R/W-0
CS1
R/W-0
CS0
R/W-1
R/W-1
LCDEN
SLPEN
WERR
VLCDEN
LMUX1
LMUX0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
C = Only clearable bit
-n = Value at POR
bit 7
bit 6
bit 5
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is disabled
SLPEN: LCD Driver Enable in Sleep mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while the WA bit of the LCDPS register = 0 (must be cleared in
software)
0= No LCD write error
bit 4
VLCDEN: LCD Bias Voltage Pins Enable bit
1= VLCD pins are enabled
0= VLCD pins are disabled
bit 3-2
CS<1:0>: Clock Source Select bits
00= FOSC/8192
01= T1OSC (Timer1)/32
1x= LFINTOSC (31 kHz)/32
bit 1-0
LMUX<1:0>: Commons Select bits
Maximum Number of Pixels
LMUX<1:0>
Multiplex
Bias
PIC16F913/916
PIC16F914/917
PIC16F946
00
01
10
11
Static (COM0)
1/2 (COM<1:0>)
1/3 (COM<2:0>)
1/4 (COM<3:0>)
16
32
24
48
72
96
42
84
Static
1/2 or 1/3
1/2 or 1/3
1/3
48
60(1)
126
168
Note 1: On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64
pixels.
© 2007 Microchip Technology Inc.
DS41250F-page 145
MICROCHIP [ MICROCHIP ]
