PIC16F913/914/916/917/946
9.4.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
9.4
AUSART Operation During Sleep
The AUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the neces-
sary signals to run the Transmit or Receive Shift regis-
ters during Sleep.
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Transmission
(see Section 9.3.2.2 “Synchronous Slave
Transmission Set-up:”).
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
•
The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
9.4.1
SYNCHRONOUS RECEIVE DURING
SLEEP
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 9.3.2.4 “Synchronous Slave
Reception Set-up:”).
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit is also set then the Interrupt Service
Routine at address 0004h will be called.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
© 2007 Microchip Technology Inc.
DS41250F-page 141
MICROCHIP [ MICROCHIP ]
