PIC16F87/88
FIGURE 18-18:
A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 18-14: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
130
TAD
A/D clock period PIC16F87/88
1.6
3.0
2.0
3.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF ≥ 2.0V
µs A/D RC mode
µs A/D RC mode
TAD
PIC16LF87/88
PIC16F87/88
PIC16LF87/88
4.0
6.0
—
6.0
9.0
12
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
(Note 2)
10*
40
—
—
—
µs
µs The minimum time is the
amplifier settling time. This may be
used if the “new” input voltage has
not changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the
SLEEPinstruction to be executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 189
MICROCHIP [ MICROCHIP ]
