PIC16F882/883/884/886/887
FIGURE 8-2:
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0>
C1POL
2
To
Data Bus
D
Q
Q1
C12IN0-
EN
0
RD_CM1CON0
Set C1IF
C12IN1-
C12IN2-
C12IN3-
1
MUX
2
D
Q
Q3*RD_CM1CON0
Reset
EN
To PWM Logic
3
CL
(1)
C1ON
C1
C1R
C1VIN-
C1VIN+
-
C1IN+
0
MUX
1
C1OUT
+
C1OUT (to SR Latch)
FixedRef
0
C1POL
MUX
1
CVREF
C1VREF
C1RSEL
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
FIGURE 8-3:
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2POL
To
D
Q
Data Bus
Q1
EN
RD_CM2CON0
C2CH<1:0>
Set C2IF
2
D
Q
Q3*RD_CM2CON0
EN
(1)
C2ON
C2
C12IN0-
0
CL
Reset
C12IN1-
C2IN2-
C2IN3-
1
MUX
2
C2VIN-
C2VIN+
C2OUT
3
C2SYNC
C2POL
0
MUX
SYNCC2OUT
C2R
D
Q
1
To Timer1 Gate, SR Latch
and other peripherals
C2IN+
0
MUX
1
From Timer1
Clock
FixedRef
0
MUX
1
CVREF
C2VREF
C2RSEL
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
DS41291D-page 84
Preliminary
© 2007 Microchip Technology Inc.
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