PIC16F882/883/884/886/887
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
11.6.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 11-9). This mode can be used for Half-Bridge
applications, as shown in Figure 11-9, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
FIGURE 11-8:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Period
Period
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWM1CON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 11.6.6 “Programmable Dead-Band Delay
Mode” for more details of the dead-band delay
operations.
(2)
(2)
P1A
td
td
P1B
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 11-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
-
P1A
Load
FET
Driver
+
-
P1B
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
© 2007 Microchip Technology Inc.
Preliminary
DS41291D-page 135
MICROCHIP [ MICROCHIP ]
