PIC16F818/819
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
U-0
—
U-0
—
U-0
—
R/W-0
EEIE
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EEIE: EEPROM Write Operation Interrupt Enable bit
1= Enable EE write interrupt
0= Disable EE write interrupt
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
.
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
U-0
—
U-0
—
U-0
—
R/W-0
EEIF
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EEIF: EEPROM Write Operation Interrupt Enable bit
1= Enable EE write interrupt
0= Disable EE write interrupt
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
DS39598E-page 21
MICROCHIP [ MICROCHIP ]
