PIC16F818/819
2.2.2.5
PIR1 Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
PIR1:PERIPHERALINTERRUPTREQUEST(FLAG)REGISTER1(ADDRESS0Ch)
U-0
—
R/W-0
ADIF
U-0
—
U-0
—
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
bit 5-4
bit 3
Unimplemented: Read as ‘0’
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1= The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are a transmission/
reception has taken place.
0= No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 20
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
