PIC16F818/819
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on Detailson
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
page:
Bank 2
100h(1) INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
—
23
53
23
16
23
—
43
—
—
—
23
18
25
25
25
25
101h
102h(1
TMR0
PCL
Program Counter’s (PC) Least Significant Byte
103h(1) STATUS
104h(1) FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
105h
106h
107h
108h
109h
—
PORTB
PORTB Data Latch when written; PORTB pins when read
xxxx xxxx
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
10Ah(1,2) PCLATH
10Bh(1) INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE TMR0IF INTF
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- -xxx
GIE
PEIE
TMR0IE
RBIF
10Ch
10Dh
10Eh
10Fh
EEDATA
EEADR
EEPROM/Flash Data Register Low Byte
EEPROM/Flash Address Register Low Byte
EEDATH
EEADRH
—
—
—
—
EEPROM/Flash Data Register High Byte
—
—
—
EEPROM/Flash Address Register
High Byte
Bank 3
180h(1) INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
23
17, 54
23
181h
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
182h(1) PCL
183h(1) STATUS
184h(1) FSR
PD
Z
DC
C
0001 1xxx
xxxx xxxx
—
16
23
—
43
—
—
—
23
18
26
25
—
—
Indirect Data Memory Address Pointer
Unimplemented
185h
186h
187h
188h
189h
—
TRISB
PORTB Data Direction Register
Unimplemented
1111 1111
—
—
—
—
Unimplemented
—
Unimplemented
—
18Ah(1,2) PCLATH
18Bh(1) INTCON
—
—
PEIE
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
x--x x000
---- ----
0000 0000
0000 0000
GIE
INTE
RBIE
TMR0IF
WREN
INTF
WR
RBIF
RD
18Ch
18Dh
18Eh
18Fh
EECON1
EECON2
—
EEPGD
FREE
WRERR
EEPROM Control Register 2 (not a physical register)
Reserved; maintain clear
—
Reserved; maintain clear
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
2:
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3:
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS39598E-page 15
MICROCHIP [ MICROCHIP ]
