PIC16F818/819
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on Detailson
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
page:
Bank 0
00h(1)
01h
02h(1)
03h(1)
04h(1)
05h
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxx0 0000
xxxx xxxx
—
23
53, 17
23
Program Counter’s (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
16
Indirect Data Memory Address Pointer
23
PORTA
PORTB
—
PORTA Data Latch when written; PORTA pins when read
PORTB Data Latch when written; PORTB pins when read
Unimplemented
39
06h
43
07h
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah(1,2) PCLATH
—
GIE
—
—
PEIE
ADIF
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
-0-- 0000
---0 ----
xxxx xxxx
xxxx xxxx
23
0Bh(1)
0Ch
0Dh
0Eh
INTCON
PIR1
INTE
—
RBIE
SSPIF
—
TMR0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
TMR1IF
—
18
20
PIR2
—
—
EEIF
21
TMR1L
TMR1H
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
57
0Fh
57
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON --00 0000
57
63
Timer2 Module Register
0000 0000
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
64
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
0000 0000
71, 76
73
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
xxxx xxxx 66, 67, 68
xxxx xxxx 66, 67, 68
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000
65
—
—
—
—
—
—
81
81
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
ADRESH
ADCON0
A/D Result Register High Byte
ADCS1 ADCS0 CHS2
xxxx xxxx
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
2:
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
3:
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS39598E-page 13
MICROCHIP [ MICROCHIP ]
