PIC16F818/819
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations as indicated in
Table 12-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires
approximately 5-10 µs to become ready for code
execution. This delay runs in parallel with any other
timers. See Table 12-4 for a full description of Reset
states of all registers.
12.2 Reset
The PIC16F818/819 differentiates between various
kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT wake-up during Sleep
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 12-1.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
Sleep
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1
PWRT
10-bit Ripple Counter
INTRC
31.25 kHz
Enable PWRT
Enable OST
2004 Microchip Technology Inc.
DS39598E-page 91
MICROCHIP [ MICROCHIP ]
