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PIC16F818-I/P 参数 Datasheet PDF下载

PIC16F818-I/P图片预览
型号: PIC16F818-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F818/819  
Timer0 module means that there is no prescaler for the  
Watchdog Timer and vice versa. This prescaler is not  
readable or writable (see Figure 6-1).  
6.3  
Using Timer0 with an  
External Clock  
When no prescaler is used, the external clock input is  
the same as the prescaler output. The synchronization  
of T0CKI with the internal phase clocks is accom-  
plished by sampling the prescaler output on the Q2 and  
Q4 cycles of the internal phase clocks. Therefore, it is  
necessary for T0CKI to be high for at least 2 TOSC (and  
a small RC delay of 20 ns) and low for at least 2 TOSC  
(and a small RC delay of 20 ns). Refer to the electrical  
specification of the desired device.  
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)  
determine the prescaler assignment and prescale ratio.  
When assigned to the Timer0 module, all instructions  
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,  
BSF  
1, x....etc.) will clear the prescaler. When  
assigned to WDT, a CLRWDT instruction will clear the  
prescaler along with the Watchdog Timer. The  
prescaler is not readable or writable.  
Note:  
Writing to TMR0 when the prescaler is  
assigned to Timer0 will clear the prescaler  
count but will not change the prescaler  
assignment.  
6.4  
Prescaler  
There is only one prescaler available which is mutually  
exclusively shared between the Timer0 module and the  
Watchdog Timer. A prescaler assignment for the  
REGISTER 6-1:  
OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h)  
R/W-1  
RBPU  
R/W-1  
R/W-1  
T0CS  
R/W-1  
T0SE  
R/W-1  
PSA  
R/W-1  
PS2  
R/W-1  
PS1  
R/W-1  
PS0  
INTEDG  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2-0  
RBPU: PORTB Pull-up Enable bit  
1= PORTB pull-ups are disabled  
0= PORTB pull-ups are enabled by individual port latch values  
INTEDG: Interrupt Edge Select bit  
1= Interrupt on rising edge of RB0/INT pin  
0= Interrupt on falling edge of RB0/INT pin  
T0CS: TMR0 Clock Source Select bit  
1= Transition on T0CKI pin  
0= Internal instruction cycle clock (CLKO)  
T0SE: TMR0 Source Edge Select bit  
1= Increment on high-to-low transition on T0CKI pin  
0= Increment on low-to-high transition on T0CKI pin  
PSA: Prescaler Assignment bit  
1= Prescaler is assigned to the WDT  
0= Prescaler is assigned to the Timer0 module  
PS2:PS0: Prescaler Rate Select bits  
Bit Value TMR0 Rate WDT Rate  
000  
001  
010  
011  
100  
101  
110  
111  
1 : 2  
1 : 4  
1 : 8  
1 : 16  
1 : 32  
1 : 64  
1 : 128  
1 : 256  
1 : 1  
1 : 2  
1 : 4  
1 : 8  
1 : 16  
1 : 32  
1 : 64  
1 : 128  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
Note:  
To avoid an unintended device Reset, the instruction sequence shown in the  
“PICmicro® Mid-Range MCU Family Reference Manual” (DS33023) must be  
executed when changing the prescaler assignment from Timer0 to the WDT. This  
sequence must be followed even if the WDT is disabled.  
DS39598E-page 54  
2004 Microchip Technology Inc.