PIC16F818/819
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-3:
BLOCK DIAGRAM OF
RA2/AN2/VREF- PIN
Data
Bus
Data
D
Q
Q
Bus
D
Q
Q
VDD
VDD
P
WR
PORTA
VDD
VDD
P
WR
PORTA
CK
CK
Data Latch
Data Latch
D
Q
D
Q
I/O pin
WR
TRISA
N
I/O pin
N
WR
CK
Q
TRISA
VSS
VSS
CK
Q
TRIS Latch
VSS
VSS
TRIS Latch
Analog
Input Mode
Analog
Input Mode
TTL
Input Buffer
TTL
Input Buffer
RD TRISA
RD TRISA
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
To A/D Module VREF- Input
To A/D Module Channel Input
To A/D Module Channel Input
FIGURE 5-2:
BLOCK DIAGRAM OF
RA3/AN3/VREF+ PIN
FIGURE 5-4:
BLOCK DIAGRAM OF
RA4/AN4/T0CKI PIN
Data
Data
Bus
Bus
D
Q
Q
D
Q
Q
VDD
VDD
P
VDD
VDD
P
WR
PORTA
WR
PORTA
CK
CK
Data Latch
Data Latch
D
Q
D
Q
I/O pin
I/O pin
WR
TRISA
WR
TRISA
N
N
CK
CK
Q
Q
VSS
VSS
VSS
TRIS Latch
TRIS Latch
VSS
Analog
Input Mode
Analog
Input Mode
TTL
Input Buffer
Schmitt Trigger
Input Buffer
RD TRISA
RD TRISA
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
To A/D Module VREF+ Input
To A/D Module Channel Input
TMR0 Clock Input
To A/D Module Channel Input
DS39598E-page 40
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
